The present invention relates generally to a method of manufacturing a semiconductor device having a dual damascene structure in which a via for electrically coupling a lower wiring layer and an upper wiring layer and the upper wiring layer are buried within an interlayer insulating film. More particularly, the present invention relates to a photo mask used when a via hole for forming a via and a wiring trench or groove for forming the wiring conductor of the upper wiring layer are opened, and to a method of manufacturing a semiconductor device which uses such photo mask.
According to an increase in an integration degree and a packing density of a semiconductor device, a dual damascene structure has become often used. In the dual damascene structure, a via for electrically coupling a lower wiring layer and an upper wiring layer and a wiring conductor of the upper wiring layer are buried within an interlayer insulating film. In the dual damascene structure, a via hole which is an opening for forming a via that electrically couples with a lower wiring layer and a wiring trench or groove for forming a wiring conductor of an upper wiring layer that extends in an area including the via are formed one after another in an interlayer insulating film by using a photolithography technology. Thereafter, the opening of the via hole and the wiring groove are filled with a wiring material. The upper surface of the workpiece substrate is then polished flat and the wiring material on the interlayer insulating film is removed. Such manufacturing method is described, for example, in Japanese patent laid-open publication No. 2000-150641.
FIGS. 9A-9E are cross sectional views each illustrating a structure of a workpiece obtained during a process of fabricating a dual damascene structure according to a conventional technology, which is substantially the same as the technology described in the above-mentioned Japanese patent laid-open publication.
First, as shown in FIG. 9A, a groove formed in a base insulating film or layer 121 on a semiconductor substrate not shown in the drawing is filled with a metal such as copper and the like, and the upper surface is planarized or flattened to form a lower wiring layer 122 having predetermined wiring patterns. On the lower wiring layer 122, an Si3N4 film 123, an SiO2 film 124, an SiC film 125, an HSQ film 126 and an SiO2 film 127 are formed one after another in this order, thereby an interlayer insulating film 128 comprising these film is formed.
As shown in FIG. 9B, by using a first photolithography process in which a first photo resist PR11 is used, the interlayer insulating film 128 is selectively etched to form a via hole 129 in an area where a via or a via conductor is to be formed such that the via hole 129 reaches the Si3N4 film 123.
Next, as shown in FIG. 9C, by using a second photolithography process in which a second photo resist PR12 is used, the interlayer insulating film 128 is selectively etched to form a wiring groove 130 in a predetermined area which includes the via hole 129 and where the wiring groove 130 is to be formed such that the wiring groove 130 reaches the SiC film 125.
Thereafter, to obtain the structure shown in FIG. 9D, the portion of the Si3N4 film 123 at the bottom surface of the via hole 129 is selectively etched and removed to expose the surface of the lower wiring layer 22. A wiring material 131 comprising a metal such as copper and the like is sputtered on whole area of the workpiece to fill the via hole 129 and the wiring groove 130 with the metal. Then, the surface of the workpiece is planarized by using a CMP (chemical mechanical polishing) method, and a structure is obtained in which the wiring material 131 remains and is buried only within the via hole 129 and the wiring groove 130. Thereby, the via 132 which is electrically coupled with the lower wiring layer 122 and the upper wiring layer 133 which is electrically coupled with the via 132 and thus the lower wiring layer 122 are formed.
In this way, when the dual damascene structure is fabricated, the first and second photolithography processes are required. Therefore, in the first photolithography process, an alignment technology is required in which the location or position of the via hole 129 is aligned with respect to the location of the lower wiring layer 22. Also, in the second photolithography process, an alignment technology is required in which the location of the wiring groove 130 is aligned with respect to the location of the via hole 129. In order to perform these alignment, it is necessary to provide alignment marks in first and second photo masks which are used for exposing, developing and patterning first and second photo resist films used in the first and second photolithography processes, respectively. In the first photolithography process, the alignment mark of the first photo mask is aligned with a lower layer alignment mark which is formed simultaneously with the lower wiring layer. In the second photolithography process, the alignment mark of the second photo mask is aligned with an alignment hole which is formed simultaneously with the via hole by using the alignment mark of the first photo mask.
FIG. 10A is a schematic plan view showing an alignment mark used when an alignment is performed in the first photolithography process. FIG. 10B is a cross sectional view of a workpiece of a semiconductor device formed by using the alignment mark of FIG. 10A. FIG. 10C is a cross sectional view illustrating a via alignment hole formed simultaneously with a via hole in the first photolithography process.
As shown in FIGS. 10A and 10B, by using a part of the lower wiring layer 122, a lower layer alignment mark DM11 is previously formed which has a square frame like shape. Also, in the first photo mask, a first via alignment mark M11 is formed which has a square shape and which is to be located at the central position of the lower layer alignment mark DM11. By using the first photo mask, the first photolithography process is performed, and by using the first photo resist pattern PR11 which is obtained by exposing and developing the first photo resist, the via hole 129 is opened in the interlayer insulating film 128. In this case, the first photo resist pattern PR11 formed by the first via alignment mark M11 and the lower layer alignment mark DM11 are optically scanned by a misalignment measuring equipment or apparatus in a direction shown by an arrow S11 in FIG. 10A. The reflection of light obtained from the optical scanning is detected and a signal output V11 shown in the upper portion of FIG. 10B is obtained. Based on the signal output V11, a relative locational difference between the central location C21 of the first photo resist pattern PR11 by the first via alignment mark M11 and the central location C22 of the lower layer alignment mark DM11 is detected, and thereby alignment between the first via alignment mark M11 and the lower layer alignment mark DM11 is performed.
FIG. 11A is a schematic plan view showing an alignment mark used when an alignment is performed in the second photolithography process. FIG. 11B is a cross sectional view of a workpiece of a semiconductor device formed by using the alignment mark of FIG. 11A. FIG. 11C is a cross sectional view illustrating a upper layer alignment hole formed simultaneously with a wiring groove in the second photolithography process.
In this case, as shown in FIGS. 11A and 11B, in the first photo mask used in the first photolithography process, a second via alignment mark M12 is previously formed which has a square frame like shape. Thereby, the second via alignment hole MH12 is opened in the interlayer insulating film 128 simultaneously with the forming of the via hole 129. Also, in the second photo mask, an upper layer alignment mark UM11 is formed which has a square shape and which is to be located at the central position of the frame of the second via alignment mark MH12. By using the second photo mask, the second photolithography process is performed, and the second photo resist pattern PR12 is formed. By the etching which uses the second photo resist pattern PR12, the wiring groove is opened which reaches the SiC film 125 of the interlayer insulating film 128. In this case, the second via alignment hole MH12 and the second photo resist pattern PR12 formed by the upper layer alignment mark UM are optically scanned by a misalignment measuring equipment in a direction shown by an arrow S12 in FIG. 11A. The reflection of light obtained from the optical scanning is detected and a signal output V12 shown in the upper portion of FIG. 11B is obtained. Based on the signal output V12, a relative locational difference between the central location C31 of the second via alignment hole MH12 and the central location C32 of the second photo resist pattern PR12 is detected, and thereby alignment between the second via alignment hole MH12 and the second photo resist pattern PR12 is performed.
In the above-mentioned alignment in the first photolithography process, since the width of the first via alignment mark M11 is approximately 1.0 xcexcm and is relatively large, when the reflected light is detected from the via alignment mark in the process of alignment, the reflection of light at the via alignment mark becomes gradual and it is difficult to detect the peak of the output signal V11. As a result, it becomes difficult to perform precise alignment. Also, as shown in FIG. 10C, since the width of the first via alignment mark M11 is relatively large, a via alignment hole MH11 which is formed in the interlayer insulating film 128 simultaneously with the via hole 129 in the first photolithography process has a smaller aspect ratio with respect to the film thickness of approximately 1.0 xcexcm of the interlayer insulating film 128 than the aspect ratio of a usual or proper via hole. Therefore, etching progresses rapidly, and when the first photolithography process is performed, the Si3N4 film 123 as an etch stopper film is also etched and over etching occurs into a base insulating film 121 at the lower layer. In this way, when the via alignment hole having a large width is formed into the interlayer insulating film 128 deeply, the following disadvantage occurs. That is, when the wiring material 131 is buried into the via alignment hole MH11, the surface portion of the via alignment hole MH11 becomes concave. It is sometimes impossible to remove such concave portion even by using the CMP process and, therefore, slurry produced in the CMP process gathers in the concave portion, or air is confined in the concave portion in a later process. In such case, moisture and/or air in the slurry expand in a heat treatment process performed later, and sometimes cause damage such as cracking of the interlayer insulating film 128 and the like. Also, due to the concavity, there occurs a difference in height between the concave portion and the peripheral area and such difference sometimes has an influence on the pattern accuracy in a photolithography process thereafter.
In the above-mentioned alignment in the second photolithography process, the width of the second via alignment mark M12 is relatively large and the width of the upper layer alignment mark UM11 is relatively large. Therefore, similarly to the first photolithography process, when the alignment is performed, the reflection of light by the upper layer alignment mark UM at the second photo resist pattern PR12 becomes gradual and it is difficult to detect the peak of the output signal V12. As a result, it becomes difficult to perform precise alignment. Also, as shown in FIG. 11C, since, in the second photolithography process, the upper layer alignment hole UH11 having a relatively large width is opened or formed in the interlayer insulating film 128 simultaneously with the opening of the wiring groove 130. Therefore, when the wiring material 131 is buried into the upper layer alignment hole UH11, the surface portion of the upper layer alignment hole UH11 becomes concave. Due to such concavity, in the second photolithography process, disadvantages similar to those in the first photolithography process arise. Also, the second via alignment hole MH12 has a relatively large width. Therefore, when, as shown in FIG. 11B, an anti-reflection film NR11 is coated as a lower layer film of the second photo resist pattern PR12 in the second photolithography process, a large quantity of material of the anti-reflection film NR11 flows into the second via alignment hole MH12. As a result, there is produced unevenness in the particular area of the interlayer insulating film 128, and also there is produced coating spot or unevenness between the particular area and the peripheral area, so that there arises a possibility that the shape of the patterns of the photo resist formed thereafter is deteriorated.
Therefore, it is an object of the present invention to provide a photo mask and a method of manufacturing a semiconductor device using the photo mask which provides a high alignment precision in semiconductor manufacturing.
It is another object of the present invention to provide a photo mask and a method of manufacturing a semiconductor device using the photo mask in which a concave portion and a difference in step height are not produced in a wiring material portion at an alignment hole and the like.
It is still another object of the present invention to provide a photo mask and a method of manufacturing a semiconductor device using the photo mask in which a precision of patterning in a photolithography process in a later process is not deteriorated.
It is still another object of the present invention to obviate the disadvantages of a conventional photo mask and a conventional method of manufacturing a semiconductor device using the photo mask.
According to an aspect of the present invention, there is provided a photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via, the via and the upper wiring layer being fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material, the photo mask having: a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer; wherein the width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole.
In this case, it is preferable that the via alignment mark comprises two sets of straight line shaped strips, one set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in X direction in a plane and the other set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in Y direction in the same plane.
It is also preferable that the two sets of straight line shaped strips are disposed parallel to a lower layer alignment mark which is formed simultaneously with the lower wiring layer.
It is further preferable that one set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in X direction and the other set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in Y direction, such that the four frame like patterns constitute a square or a rectangular shape.
It is advantageous that the via alignment mark comprises a frame like square or rectangular shaped strip.
According to another aspect of the present invention, there is provided a photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via, the via and the upper wiring layer being fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material, the photo mask having: a via alignment mark which is used for aligning the wiring groove with respect to the via hole; wherein the width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole.
In this case, it is preferable that the via alignment mark comprises two sets of straight line shaped strips, one set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in X direction in a plane and the other set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in Y direction in the same plane.
It is also preferable that the two sets of straight line shaped strips are disposed parallel to an upper layer alignment mark which is formed simultaneously with the upper wiring layer.
It is further preferable that one set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in X direction and the other set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in Y direction, such that the four frame like patterns constitute a square or a rectangular shape.
It is advantageous that the via alignment mark comprises a frame like square or rectangular shaped strip.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a dual damascene structure, the method comprising: forming a via hole in an interlayer insulating film formed on a lower wiring layer; forming a wiring groove in the interlayer insulating film which includes the via hole; filling the via hole and the wiring groove with a wiring material; flattening the surface of the wiring material together with the surface of the interlayer insulating film such that the wiring material remains in the via hole and the wiring groove, thereby forming a via and an upper wiring layer; wherein, in forming the via hole in the interlayer insulating film formed on the lower wiring layer, the via hole is formed by a photolithography process that uses a photo mask having a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer; and wherein the width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole.
In this case, it is preferable that the via alignment mark comprises two sets of straight line shaped strips, one set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in X direction in a plane and the other set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in Y direction in the same plane.
It is also preferable that the two sets of straight line shaped strips are disposed parallel to a lower layer alignment mark which is formed simultaneously with the lower wiring layer.
It is further preferable that one set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in X direction and the other set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in Y direction, such that the four frame like patterns constitute a square or a rectangular shape.
It is advantageous that the via alignment mark comprises a frame like square or rectangular shaped strip.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a dual damascene structure, the method comprising: forming a via hole in an interlayer insulating film formed on a lower wiring layer; forming a wiring groove in the interlayer insulating film which includes the via hole; filling the via hole and the wiring groove with a wiring material; flattening the surface of the wiring material together with the surface of the interlayer insulating film such that the wiring material remains in the via hole and the wiring groove, thereby forming a via and an upper wiring layer; wherein, when forming the wiring groove in an interlayer insulating film which includes the via hole, the wiring groove is formed by a photolithography process that uses a photo mask having a via alignment mark which is used for aligning the wiring groove with respect to the via hole; wherein the width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole.
In this case, it is preferable that the via alignment mark comprises two sets of straight line shaped strips, one set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in X direction in a plane and the other set of the straight line shaped strips having at least a pair of straight line shaped patterns which are opposed to each other in Y direction in the same plane.
It is also preferable that the two sets of straight line shaped strips are disposed parallel to an upper layer alignment mark which is formed simultaneously with the upper wiring layer.
It is further preferable that one set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in X direction and the other set of the straight line shaped strips comprises a pair of frame like patterns each of which has an elongated rectangular frame shape and which are opposed to each other in Y direction, such that the four frame like patterns constitute a square or a rectangular shape.
It is advantageous that the via alignment mark comprises a frame like square or rectangular shaped strip.
According to the above-mentioned aspects of the present invention, each of the via alignment marks is constituted of strips (or slits) each having a minute width. Therefore, it is possible to detect, for example, by an optical detecting method, the central location or position between the strips, that is, the central position between the via alignment marks, with high precision, and to perform alignment of the lower layer alignment mark and the upper layer alignment mark with high precision. Also, each of the alignment holes formed by using the via alignment mark has a minute width and has an aspect ratio close to an aspect ratio of proper via holes. Therefore, etching of the alignment holes does not progress more rapidly than etching of the proper via holes, and the lower layer insulating film is not over-etched. Thus, the interlayer insulating film in the areas near the alignment holes is not etched excessively, and undesirable unevenness of the upper surface of the interlayer insulating film does not occur in such areas with respect to the peripheral area thereof. Further, when the alignment holes are filled with wiring material such as copper and the like and the interlayer insulating film is flattened by the CMP process and the like, concave portions are not produced at the upper surface portions of the alignment holes. Therefore, the surface of the interlayer insulating film becomes flat, and pattern accuracy and the like in a photolithography process thereafter is not deteriorated by the unevenness of the surface of the workpiece. Further, slurry and/or air do not remain in the concave portion. As a result, it becomes possible to fabricate semiconductor devices having high reliability.